Electrically programmable semiconductor memories (hereinafter, abbreviated as EPROMs including an electrically erasable and programmable device) recently have been widely produced. The memory is called an EPROM has a structure similar to a FET and is provided with a gate electrode between both impurity layers of the source and the drain. Unlike the ordinary FET, the gate electrode has a multi-layer structure. An insulation film is interposed between the semiconductor layers, called the floating gate electrodes, and moreover a semiconductor layer called a control gate is layered.
A recent process producing EPROM's has almost been carried out based on self-alignment. In this self-alignment based process, a gate electrode is formed with polysilicon, etc., on the surface of an element forming region of the semiconductor substrate. The gate electrode itself is used as the mask when impurity ions are implanted in the substrate and the source, and drain regions are formed in both sides of the gate electrode. In recent micro-miniaturized EPROMs, the self-alignment method using the gate electrode itself as the mask is particularly effective because the positioning margin to form the mask used for ion implantation is no longer necessary, when compared with conventional methods in which the ion implantation has been conducted without using the self-alignment method.
However, with the present self-alignment process, it is important to always form the source and drain in the regulated width in order to ensure good controllability of the channel region width between the source and drain regions to minimize variation of characteristics of each EPROM completed in each process. In the self-alignment source and drain region forming method, after a gate electrode is formed on the surface of the semiconductor substrate through an oxide film, the gate electrode itself is used as the mask for impurity ion implantation. Improvement of controllability of the source and drain width depends on whether or not the side surface of gate electrode, which is used as a mask, is always formed with the same shape. For example, if any substance adheres to the side surface of the gate electrode or adheres to any partial side during the process, etching is unexpectedly generated, so that when the gate electrode is later used as the mask, the source and drain cannot always be formed in the desired position on the surface of semiconductor substrate. When deposition or partial etching at the side surface is always uniform, it may be allowed to occur, but the side surface of the gate electrode is actually always non-uniform.
Since recent EPROMs are more and more micro-miniaturized, the controllability, namely how to always uniformly produce EPROMs with the same characteristics, is a very important problem since it influences the yield. In the self-alignment process, since ion implantation to form the source and drain regions is carried out with the previously formed gate electrode itself used as the mask, the source and drain must always be formed with the same shape on the side surface of the gate electrode, which is used as the mask, in order to improve controllability in formation of the source and drain regions.
The process of producing conventional EPROMs will first be explained with reference to FIG. 2a through FIG. 2c.
FIGS. 2 are diagrams for explaining the processes indicating conventional EPROM producing technology. In these figures, the numeral 1 designates a semiconductor substrate of a single crystal silicon. A first oxide film 10 is formed on the surface of the semiconductor substrate 1 and a first polycrystal silicon layer 11 is formed by a vapor growth method on the surface of the first oxide film 10. A second oxide film 20 is formed by thermal oxidation on the surface of the first polycrystal silicon layer 11 and a second polycrystal silicon layer (not shown) is formed by the vapor growth method on the surface the second oxide film 20. A photoresist 3 as the mask for the pattern to form the gate is partially formed on the surface of the second polycrystal silicon layer.
Referring to FIGS. 3a-3b for comparison, FIG. 3a is a plan view of the EPROM gate electrode produced by the prior art, while FIG. 3b is a plan view of the EPROM gate electrode produced by the present invention.
The process is sequentially explained hereunder.
In FIG. 2a, after the second polycrystal silicon layer is layered on the surface of the substrate as described previously, it is selectively removed to form the control gate electrode 211 by RIE (reactive ion etching using, for example, sulfur hexafluoride (SF.sub.6) gas or tetracarbon chloride (CCl.sub.4) gas) and the mask material 3 formed as described above in order to expose the second oxide film 20.
In FIG. 2b, using the same mask material as that used in the preceding process, the second oxide film 20 is selectively removed to form the gate electrode 201, for example, by RIE using methane trifluoride (CHF.sub.3) gas in order to expose the first polycrystal silicon layer 11. Thereafter, the unwanted first polycrystal silicon 11 is removed by etching with RIE using SF.sub.6 (sulfur hexafluoride) gas to form layer 111 and the unwanted first oxide film 10 is removed by wet chemical etching with a solution containing HF (fluoric acid) to form the gate oxide film 101. The mask material 3 is removed and after the end of this etching process, the up-diffused control gate electrode 211 is formed in the side surface. In this case, a thin film 30 is non-uniformly deposited to an average thickness of about 100 .ANG. at the side surface of the second polycrystal silicon layer left after the etching. This thin film is thought to be formed by a silicon compound produced by reaction of the etching gas and an intermediate product of silicon forming an oxide film but it is not clear. This thin film 30 is very thin and deposited non-uniformly. Therefore, it is partly as thin as can be as though nothing is deposited, but it is partly thick enough. The thin film 30 is also obvious from FIG. 3a.
When etching the polycrystal silicon 11 with the RIE method using a gas containing sulfur hexafluoride (SF.sub.6) having selective isotropic characteristics, the side surface of the gate 111 is etched as shown in FIG. 2c. Etching in the lateral direction of the gate electrode with the RIE method sulfur hexafluoride (SF.sub.6) is about 0.1-0.3 .mu.m when the gate electrode is 3000-4000 .ANG. thick. Etching in the lateral direction of the gate electrode, mentioned above, is also observed when etching with the RIE method using other gaseous etchants.
As explained previously, since the thin film 30 has a non-uniform thickness, partly has holes and is deposited on the side surface of the control gate electrode, the areas having the holes are selectively etched. Accordingly, after the RIE method to form the floating gate electrode, the side surface of the control gate electrode becomes uneven.
As described above, according to the conventional method of producing EPROMs, as shown in FIG. 3a, the side surface of control gate electrode, to be used as the mask for implantation of impurity ions, becomes rough and does not always have the same shape in each production process. The source and drain regions formed with such an electrode used as the mask cannot provide EPROMs having the same characteristics in every process. In the worse case, the characteristics of the EPROMs may be so deteriorated that they cannot be put into practical use, and therefore, influence the production yield. This problem of the prior art will become more serious with further micro-miniaturization of the gate electrode itself in the future.
In other prior art, etching of oxide film sandwiched by the gate electrodes can be done by a chemical wet etching method instead of RIE. In this case, after the upper control gate electrode is removed by RIE, the entire substrate is removed from the RIE chamber and the oxide film is exposed to a thin aqueous solution of HF (fluoric acid). Thereafter, the substrate is again returned into the RIE chamber. However, according to this method, since the entire substrate must be removed from the chamber in order to etch the oxide film, the substrate surface is naturally exposed to oxygen and the oxide film is probably formed particularly in the area in which silicon is exposed. Since the etchants as well as the thin aqueous solution of HF have the property to anisotropically proceed etching, the oxide film is also etched in the internal direction of the gate during etching of the oxide film. In the case of wet chemical etching, the end point of the etching cannot be detected accurately. Therefore, if the substrate is continuously soaked in the etchant even after all the desired oxide film is removed, the oxide film between the gate electrodes which should not be removed, is also thereby removed. In addition, since the degree of removal cannot be detected, it is impossible to predict how much deviation will occur from the desired operation characteristic defined in the design state. Thus, it is also difficult, even with etching the oxide film with an aqueous solution of HF, to form EPROMs having the desired operation characteristics defined in the design stage.